---------- Begin Simulation Statistics ---------- final_tick 22127000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) host_inst_rate 64836 # Simulator instruction rate (inst/s) host_mem_usage 818404 # Number of bytes of host memory used host_op_rate 74597 # Simulator op (including micro ops) rate (op/s) host_seconds 0.11 # Real time elapsed on the host host_tick_rate 205149757 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6979 # Number of instructions simulated sim_ops 8044 # Number of ops (including micro ops) simulated sim_seconds 0.000022 # Number of seconds simulated sim_ticks 22127000 # Number of ticks simulated system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 55.463347 # BTB Hit Percentage system.cpu.branchPred.BTBHits 401 # Number of BTB hits system.cpu.branchPred.BTBLookups 723 # Number of BTB lookups system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.branchPred.condIncorrect 589 # Number of conditional branches incorrect system.cpu.branchPred.condPredicted 1969 # Number of conditional branches predicted system.cpu.branchPred.indirectHits 0 # Number of indirect target hits. system.cpu.branchPred.indirectLookups 77 # Number of indirect predictor lookups. system.cpu.branchPred.indirectMisses 77 # Number of indirect misses. system.cpu.branchPred.lookups 2691 # Number of BP lookups system.cpu.branchPred.usedRAS 230 # Number of times the RAS was used to get a target. system.cpu.branchPredindirectMispredicted 35 # Number of mispredicted indirect branches. system.cpu.cc_regfile_reads 2772 # number of cc regfile reads system.cpu.cc_regfile_writes 2742 # number of cc regfile writes system.cpu.commit.amos 0 # Number of atomic instructions committed system.cpu.commit.branchMispredicts 440 # The number of times a branch was mispredicted system.cpu.commit.branches 1456 # Number of branches committed system.cpu.commit.bw_lim_events 154 # number cycles where commit BW limit reached system.cpu.commit.commitNonSpecStalls 22 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 2223 # The number of squashed insts skipped by commit system.cpu.commit.committedInsts 6996 # Number of instructions committed system.cpu.commit.committedOps 8061 # Number of ops (including micro ops) committed system.cpu.commit.committed_per_cycle::samples 23825 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 0.338342 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 1.003470 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 19715 82.75% 82.75% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 2309 9.69% 92.44% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 1007 4.23% 96.67% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 300 1.26% 97.93% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 162 0.68% 98.61% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 127 0.53% 99.14% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 34 0.14% 99.28% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 17 0.07% 99.35% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 154 0.65% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 23825 # Number of insts commited each cycle system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.function_calls 110 # Number of function calls committed. system.cpu.commit.int_insts 6756 # Number of committed integer instructions. system.cpu.commit.loads 1098 # Number of loads committed system.cpu.commit.membars 14 # Number of memory barriers committed system.cpu.commit.op_class_0::No_OpClass 2 0.02% 0.02% # Class of committed instruction system.cpu.commit.op_class_0::IntAlu 5132 63.66% 63.69% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 3 0.04% 63.73% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 2 0.02% 63.75% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.75% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.75% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.75% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.75% # Class of committed instruction system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 63.75% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.75% # Class of committed instruction system.cpu.commit.op_class_0::FloatMisc 0 0.00% 63.75% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.75% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 11 0.14% 63.89% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.89% # Class of committed instruction system.cpu.commit.op_class_0::SimdAlu 108 1.34% 65.23% # Class of committed instruction system.cpu.commit.op_class_0::SimdCmp 109 1.35% 66.58% # Class of committed instruction system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.58% # Class of committed instruction system.cpu.commit.op_class_0::SimdMisc 8 0.10% 66.68% # Class of committed instruction system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.68% # Class of committed instruction system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.68% # Class of committed instruction system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.68% # Class of committed instruction system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.68% # Class of committed instruction system.cpu.commit.op_class_0::SimdDiv 0 0.00% 66.68% # Class of committed instruction system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.68% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAdd 200 2.48% 69.16% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAlu 1 0.01% 69.17% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 69.17% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 69.17% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 100 1.24% 70.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 70.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 70.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 70.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 70.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 70.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdAes 0 0.00% 70.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 70.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 70.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 70.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 70.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 70.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 70.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 70.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdPredAlu 101 1.25% 71.67% # Class of committed instruction system.cpu.commit.op_class_0::MemRead 1098 13.62% 85.29% # Class of committed instruction system.cpu.commit.op_class_0::MemWrite 1186 14.71% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 8061 # Class of committed instruction system.cpu.commit.refs 2284 # Number of memory references committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.vec_insts 782 # Number of committed Vector instructions. system.cpu.committedInsts 6979 # Number of Instructions Simulated system.cpu.committedOps 8044 # Number of Ops (including micro ops) Simulated system.cpu.cpi 6.341166 # CPI: Cycles Per Instruction system.cpu.cpi_total 6.341166 # CPI: Total CPI of All Threads system.cpu.decode.BlockedCycles 7604 # Number of cycles decode is blocked system.cpu.decode.BranchMispred 152 # Number of times decode detected a branch misprediction system.cpu.decode.BranchResolved 503 # Number of times decode resolved a branch system.cpu.decode.DecodedInsts 12027 # Number of instructions handled by decode system.cpu.decode.IdleCycles 10521 # Number of cycles decode is idle system.cpu.decode.RunCycles 5403 # Number of cycles decode is running system.cpu.decode.SquashCycles 453 # Number of cycles decode is squashing system.cpu.decode.SquashedInsts 1268 # Number of squashed instructions handled by decode system.cpu.decode.UnblockCycles 413 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.fetch.Branches 2691 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 4042 # Number of cache lines fetched system.cpu.fetch.Cycles 11637 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 332 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 12730 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 1204 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.060807 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 12155 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 631 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 0.287651 # Number of inst fetches per cycle system.cpu.fetch.rateDist::samples 24394 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 0.595556 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 1.084995 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 17714 72.62% 72.62% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 2404 9.85% 82.47% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 704 2.89% 85.36% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 3572 14.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 24394 # Number of instructions fetched each cycle (Total) system.cpu.idleCycles 19861 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.branchMispredicts 461 # Number of branch mispredicts detected at execute system.cpu.iew.exec_branches 1698 # Number of branches executed system.cpu.iew.exec_nop 33 # number of nop insts executed system.cpu.iew.exec_rate 0.224879 # Inst execution rate system.cpu.iew.exec_refs 3012 # number of memory reference insts executed system.cpu.iew.exec_stores 1283 # Number of stores executed system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 116 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 1631 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 1450 # Number of dispatched store instructions system.cpu.iew.iewDispatchedInsts 10716 # Number of instructions dispatched to IQ system.cpu.iew.iewExecLoadInsts 1729 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 440 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecutedInsts 9952 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 90 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 453 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 89 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations system.cpu.iew.lsq.thread0.rescheduledLoads 292 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.squashedLoads 533 # Number of loads squashed system.cpu.iew.lsq.thread0.squashedStores 264 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 457 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 4 # Number of branches that were predicted taken incorrectly system.cpu.iew.wb_consumers 6779 # num instructions consuming a value system.cpu.iew.wb_count 9400 # cumulative count of insts written-back system.cpu.iew.wb_fanout 0.591090 # average fanout of values written-back system.cpu.iew.wb_producers 4007 # num instructions producing a value system.cpu.iew.wb_rate 0.212405 # insts written-back per cycle system.cpu.iew.wb_sent 9471 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 10813 # number of integer regfile reads system.cpu.int_regfile_writes 5906 # number of integer regfile writes system.cpu.ipc 0.157700 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.157700 # IPC: Total IPC of All Threads system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 6519 62.73% 62.75% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 3 0.03% 62.78% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 2 0.02% 62.80% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.80% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.80% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.80% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.80% # Type of FU issued system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.80% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.80% # Type of FU issued system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.80% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 11 0.11% 62.90% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.90% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 114 1.10% 64.00% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 115 1.11% 65.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 8 0.08% 65.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 65.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 208 2.00% 67.19% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 1 0.01% 67.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 104 1.00% 68.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 68.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 68.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 68.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 68.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 68.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdAes 0 0.00% 68.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 68.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 68.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 68.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 68.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 68.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 68.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 68.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdPredAlu 107 1.03% 69.23% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 1866 17.96% 87.18% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1332 12.82% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 10392 # Type of FU issued system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fu_busy_cnt 1634 # FU busy when requested system.cpu.iq.fu_busy_rate 0.157236 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 444 27.17% 27.17% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 27.17% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 27.17% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 27.17% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 27.17% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 27.17% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 27.17% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 27.17% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 27.17% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMisc 0 0.00% 27.17% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 27.17% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 27.17% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 27.17% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 2 0.12% 27.29% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 2 0.12% 27.42% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 27.42% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 27.42% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 27.42% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 27.42% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 27.42% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 27.42% # attempts to use FU when none available system.cpu.iq.fu_full::SimdDiv 0 0.00% 27.42% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 27.42% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 2 0.12% 27.54% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 27.54% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 27.54% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 27.54% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 27.54% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 27.54% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 27.54% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.54% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 27.54% # attempts to use FU when none available system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 27.54% # attempts to use FU when none available system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 27.54% # attempts to use FU when none available system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 27.54% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 27.54% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 27.54% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAes 0 0.00% 27.54% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAesMix 0 0.00% 27.54% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 27.54% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 27.54% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 27.54% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 27.54% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 27.54% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 27.54% # attempts to use FU when none available system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 27.54% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 675 41.31% 68.85% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 509 31.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 10447 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 44195 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 8590 # Number of integer instruction queue wakeup accesses system.cpu.iq.int_inst_queue_writes 12422 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 10655 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 10392 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqSquashedInstsExamined 2638 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 82 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 1557 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.issued_per_cycle::samples 24394 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.426006 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 0.780269 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 17751 72.77% 72.77% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 3539 14.51% 87.28% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 2508 10.28% 97.56% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 547 2.24% 99.80% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 49 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 24394 # Number of insts issued each cycle system.cpu.iq.rate 0.234821 # Inst issue rate system.cpu.iq.vec_alu_accesses 1577 # Number of vector alu accesses system.cpu.iq.vec_inst_queue_reads 2699 # Number of vector instruction queue reads system.cpu.iq.vec_inst_queue_wakeup_accesses 810 # Number of vector instruction queue wakeup accesses system.cpu.iq.vec_inst_queue_writes 906 # Number of vector instruction queue writes system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.hits 0 # DTB hits system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.misses 0 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.memDep0.conflictingLoads 299 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 98 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 1631 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1450 # Number of stores inserted to the mem dependence unit. system.cpu.misc_regfile_reads 21200 # number of misc regfile reads system.cpu.misc_regfile_writes 357 # number of misc regfile writes system.cpu.numCycles 44255 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.pred_regfile_reads 1459 # number of predicate regfile reads system.cpu.pred_regfile_writes 214 # number of predicate regfile writes system.cpu.rename.BlockCycles 3528 # Number of cycles rename is blocking system.cpu.rename.CommittedMaps 8438 # Number of HB maps that are committed system.cpu.rename.IdleCycles 11523 # Number of cycles rename is idle system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full system.cpu.rename.ROBFullEvents 574 # Number of times rename has blocked due to ROB full system.cpu.rename.RenameLookups 19671 # Number of register rename lookups that rename has made system.cpu.rename.RenamedInsts 11175 # Number of instructions processed by rename system.cpu.rename.RenamedOperands 11504 # Number of destination operands rename has renamed system.cpu.rename.RunCycles 4767 # Number of cycles rename is running system.cpu.rename.SQFullEvents 1484 # Number of times rename has blocked due to SQ full system.cpu.rename.SquashCycles 453 # Number of cycles rename is squashing system.cpu.rename.SquashedInsts 420 # Number of squashed instructions processed by rename system.cpu.rename.UnblockCycles 2173 # Number of cycles rename is unblocking system.cpu.rename.UndoneMaps 3066 # Number of HB maps that are undone due to squashing system.cpu.rename.int_rename_lookups 11832 # Number of integer rename lookups system.cpu.rename.serializeStallCycles 1950 # count of cycles rename stalled for serializing inst system.cpu.rename.serializingInsts 57 # count of serializing insts renamed system.cpu.rename.skidInsts 943 # count of insts added to the skid buffer system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed system.cpu.rename.vec_pred_rename_lookups 854 # Number of vector predicate rename lookups system.cpu.rename.vec_rename_lookups 874 # Number of vector rename lookups system.cpu.rob.rob_reads 33864 # The number of ROB reads system.cpu.rob.rob_writes 21138 # The number of ROB writes system.cpu.timesIdled 246 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.vec_regfile_reads 826 # number of vector regfile reads system.cpu.vec_regfile_writes 666 # number of vector regfile writes system.cpu.workload.numSyscalls 7 # Number of system calls system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_single_requests 35 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.tot_requests 532 # Total number of requests made to the snoop filter. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.pwrStateResidencyTicks::UNDEFINED 22127000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 407 # Transaction distribution system.membus.trans_dist::WritebackClean 33 # Transaction distribution system.membus.trans_dist::ReadExReq 84 # Transaction distribution system.membus.trans_dist::ReadExResp 84 # Transaction distribution system.membus.trans_dist::ReadCleanReq 313 # Transaction distribution system.membus.trans_dist::ReadSharedReq 95 # Transaction distribution system.membus.trans_dist::InvalidateReq 7 # Transaction distribution system.membus.pkt_count_system.cpu.icache.mem_side::system.mem_ctrls.port 658 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.dcache.mem_side::system.mem_ctrls.port 365 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1023 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.icache.mem_side::system.mem_ctrls.port 22080 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.dcache.mem_side::system.mem_ctrls.port 11456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 33536 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 499 # Request fanout histogram system.membus.snoop_fanout::mean 0.004008 # Request fanout histogram system.membus.snoop_fanout::stdev 0.063245 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 497 99.60% 99.60% # Request fanout histogram system.membus.snoop_fanout::1 2 0.40% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 499 # Request fanout histogram system.membus.reqLayer0.occupancy 792500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.6 # Layer utilization (%) system.membus.respLayer1.occupancy 1660250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 7.5 # Layer utilization (%) system.membus.respLayer2.occupancy 948750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 4.3 # Layer utilization (%) system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.cpu_voltage_domain.voltage 1 # Voltage in Volts system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 22127000 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::.cpu.inst 19968 # Number of bytes read from this memory system.mem_ctrls.bytes_read::.cpu.data 11456 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 31424 # Number of bytes read from this memory system.mem_ctrls.bytes_inst_read::.cpu.inst 19968 # Number of instructions bytes read from this memory system.mem_ctrls.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory system.mem_ctrls.num_reads::.cpu.inst 312 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::.cpu.data 179 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::total 491 # Number of read requests responded to by this memory system.mem_ctrls.bw_read::.cpu.inst 902426899 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::.cpu.data 517738510 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::total 1420165409 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_inst_read::.cpu.inst 902426899 # Instruction read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_inst_read::total 902426899 # Instruction read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_total::.cpu.inst 902426899 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::.cpu.data 517738510 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::total 1420165409 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.avgPriority_.writebacks::samples 33.00 # Average QoS priority value for accepted requests system.mem_ctrls.avgPriority_.cpu.inst::samples 311.00 # Average QoS priority value for accepted requests system.mem_ctrls.avgPriority_.cpu.data::samples 179.00 # Average QoS priority value for accepted requests system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) system.mem_ctrls.priorityMaxLatency 0.000031307250 # per QoS priority maximum request to response latency (s) system.mem_ctrls.numReadWriteTurnArounds 1 # Number of turnarounds from READ to WRITE system.mem_ctrls.numWriteReadTurnArounds 1 # Number of turnarounds from WRITE to READ system.mem_ctrls.numStayReadState 992 # Number of times bus staying in READ state system.mem_ctrls.numStayWriteState 15 # Number of times bus staying in WRITE state system.mem_ctrls.readReqs 492 # Number of read requests accepted system.mem_ctrls.writeReqs 33 # Number of write requests accepted system.mem_ctrls.readBursts 492 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 33 # Number of DRAM write bursts, including those merged in the write queue system.mem_ctrls.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 50 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 3 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 27 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 6 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 27 # Per bank write bursts system.mem_ctrls.perBankRdBursts::7 19 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 52 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 31 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 43 # Per bank write bursts system.mem_ctrls.perBankRdBursts::11 81 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 48 # Per bank write bursts system.mem_ctrls.perBankRdBursts::13 79 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 20 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 3 # Per bank write bursts system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 10 # Per bank write bursts system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::13 3 # Per bank write bursts system.mem_ctrls.perBankWrBursts::14 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.avgRdQLen 1.64 # Average read queue length when enqueuing system.mem_ctrls.avgWrQLen 7.96 # Average write queue length when enqueuing system.mem_ctrls.totQLat 4251000 # Total ticks spent queuing system.mem_ctrls.totBusLat 2450000 # Total ticks spent in databus transfers system.mem_ctrls.totMemAccLat 13438500 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrls.avgQLat 8675.51 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst system.mem_ctrls.avgMemAccLat 27425.51 # Average memory access latency per DRAM burst system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry system.mem_ctrls.readRowHits 401 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 14 # Number of row buffer hits during writes system.mem_ctrls.readRowHitRate 81.84 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 42.42 # Row buffer hit rate for writes system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::6 492 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 33 # Write request sizes (log2) system.mem_ctrls.rdQLenPdf::0 278 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 141 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 55 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 14 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 2 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::17 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::18 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::19 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::20 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::21 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::22 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::23 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::24 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::25 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::26 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::27 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::28 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::29 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::30 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::31 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::32 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrls.bytesPerActivate::samples 79 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::mean 358.075949 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::gmean 238.777155 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::stdev 315.790817 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::0-127 16 20.25% 20.25% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::128-255 20 25.32% 45.57% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::256-383 17 21.52% 67.09% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::384-511 5 6.33% 73.42% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::512-639 5 6.33% 79.75% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::640-767 3 3.80% 83.54% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::768-895 2 2.53% 86.08% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::896-1023 3 3.80% 89.87% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::1024-1151 8 10.13% 100.00% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::total 79 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::mean 488 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::gmean 488.000000 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::stdev nan # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::480-495 1 100.00% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 1 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 1 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads system.mem_ctrls.bytesReadDRAM 31360 # Total number of bytes read from DRAM system.mem_ctrls.bytesReadWrQ 128 # Total number of bytes read from write queue system.mem_ctrls.bytesWritten 1024 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 31488 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 2112 # Total written bytes from the system interface side system.mem_ctrls.avgRdBW 1417.27 # Average DRAM read bandwidth in MiByte/s system.mem_ctrls.avgWrBW 46.28 # Average achieved write bandwidth in MiByte/s system.mem_ctrls.avgRdBWSys 1423.06 # Average system read bandwidth in MiByte/s system.mem_ctrls.avgWrBWSys 95.45 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrls.busUtil 11.43 # Data bus utilization in percentage system.mem_ctrls.busUtilRead 11.07 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.36 # Data bus utilization in percentage for writes system.mem_ctrls.totGap 22118500 # Total gap between requests system.mem_ctrls.avgGap 42130.48 # Average gap between requests system.mem_ctrls.masterReadBytes::.cpu.inst 19904 # Per-master bytes read from memory system.mem_ctrls.masterReadBytes::.cpu.data 11456 # Per-master bytes read from memory system.mem_ctrls.masterWriteBytes::.writebacks 1024 # Per-master bytes write to memory system.mem_ctrls.masterReadRate::.cpu.inst 899534505.355448126793 # Per-master bytes read from memory rate (Bytes/sec) system.mem_ctrls.masterReadRate::.cpu.data 517738509.513264358044 # Per-master bytes read from memory rate (Bytes/sec) system.mem_ctrls.masterWriteRate::.writebacks 46278302.526325300336 # Per-master bytes write to memory rate (Bytes/sec) system.mem_ctrls.masterReadAccesses::.cpu.inst 313 # Per-master read serviced memory accesses system.mem_ctrls.masterReadAccesses::.cpu.data 179 # Per-master read serviced memory accesses system.mem_ctrls.masterWriteAccesses::.writebacks 33 # Per-master write serviced memory accesses system.mem_ctrls.masterReadTotalLat::.cpu.inst 7951000 # Per-master read total memory access latency system.mem_ctrls.masterReadTotalLat::.cpu.data 5487500 # Per-master read total memory access latency system.mem_ctrls.masterWriteTotalLat::.writebacks 84261000 # Per-master write total memory access latency system.mem_ctrls.masterReadAvgLat::.cpu.inst 25402.56 # Per-master read average memory access latency system.mem_ctrls.masterReadAvgLat::.cpu.data 30656.42 # Per-master read average memory access latency system.mem_ctrls.masterWriteAvgLat::.writebacks 2553363.64 # Per-master write average memory access latency system.mem_ctrls.pageHitRate 79.35 # Row buffer hit rate, read and write combined system.mem_ctrls.rank1.actEnergy 471240 # Energy for activate commands per rank (pJ) system.mem_ctrls.rank1.preEnergy 235290 # Energy for precharge commands per rank (pJ) system.mem_ctrls.rank1.readEnergy 2541840 # Energy for read commands per rank (pJ) system.mem_ctrls.rank1.writeEnergy 83520 # Energy for write commands per rank (pJ) system.mem_ctrls.rank1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) system.mem_ctrls.rank1.actBackEnergy 9956760 # Energy for active background per rank (pJ) system.mem_ctrls.rank1.preBackEnergy 112320 # Energy for precharge background per rank (pJ) system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.mem_ctrls.rank1.totalEnergy 14630250 # Total energy per rank (pJ) system.mem_ctrls.rank1.averagePower 661.194468 # Core power per rank (mW) system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank system.mem_ctrls.rank1.memoryStateTime::IDLE 222750 # Time in different power states system.mem_ctrls.rank1.memoryStateTime::REF 520000 # Time in different power states system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls.rank1.memoryStateTime::ACT 21384250 # Time in different power states system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrls.rank0.actEnergy 171360 # Energy for activate commands per rank (pJ) system.mem_ctrls.rank0.preEnergy 64515 # Energy for precharge commands per rank (pJ) system.mem_ctrls.rank0.readEnergy 949620 # Energy for read commands per rank (pJ) system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrls.rank0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) system.mem_ctrls.rank0.actBackEnergy 9857010 # Energy for active background per rank (pJ) system.mem_ctrls.rank0.preBackEnergy 196320 # Energy for precharge background per rank (pJ) system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.mem_ctrls.rank0.totalEnergy 12468105 # Total energy per rank (pJ) system.mem_ctrls.rank0.averagePower 563.479234 # Core power per rank (mW) system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank system.mem_ctrls.rank0.memoryStateTime::IDLE 456000 # Time in different power states system.mem_ctrls.rank0.memoryStateTime::REF 520000 # Time in different power states system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls.rank0.memoryStateTime::ACT 21151000 # Time in different power states system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.pwrStateResidencyTicks::ON 22127000 # Cumulative time (in ticks) in various power states system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22127000 # Cumulative time (in ticks) in various power states system.cpu.icache.demand_hits::.cpu.inst 3614 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 3614 # number of demand (read+write) hits system.cpu.icache.overall_hits::.cpu.inst 3614 # number of overall hits system.cpu.icache.overall_hits::total 3614 # number of overall hits system.cpu.icache.demand_misses::.cpu.inst 428 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 428 # number of demand (read+write) misses system.cpu.icache.overall_misses::.cpu.inst 428 # number of overall misses system.cpu.icache.overall_misses::total 428 # number of overall misses system.cpu.icache.demand_miss_latency::.cpu.inst 22501500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 22501500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::.cpu.inst 22501500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 22501500 # number of overall miss cycles system.cpu.icache.demand_accesses::.cpu.inst 4042 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 4042 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::.cpu.inst 4042 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 4042 # number of overall (read+write) accesses system.cpu.icache.demand_miss_rate::.cpu.inst 0.105888 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.105888 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::.cpu.inst 0.105888 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.105888 # miss rate for overall accesses system.cpu.icache.demand_avg_miss_latency::.cpu.inst 52573.598131 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 52573.598131 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::.cpu.inst 52573.598131 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 52573.598131 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::.writebacks 33 # number of writebacks system.cpu.icache.writebacks::total 33 # number of writebacks system.cpu.icache.demand_mshr_hits::.cpu.inst 115 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 115 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::.cpu.inst 115 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 115 # number of overall MSHR hits system.cpu.icache.demand_mshr_misses::.cpu.inst 313 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::.cpu.inst 313 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 17775500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 17775500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 17775500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 17775500 # number of overall MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.077437 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.077437 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.077437 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.077437 # mshr miss rate for overall accesses system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 56790.734824 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 56790.734824 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 56790.734824 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 56790.734824 # average overall mshr miss latency system.cpu.icache.replacements 33 # number of replacements system.cpu.icache.ReadReq_hits::.cpu.inst 3614 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 3614 # number of ReadReq hits system.cpu.icache.ReadReq_misses::.cpu.inst 428 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 428 # number of ReadReq misses system.cpu.icache.ReadReq_miss_latency::.cpu.inst 22501500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 22501500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_accesses::.cpu.inst 4042 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4042 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.105888 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.105888 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 52573.598131 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 52573.598131 # average ReadReq miss latency system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 115 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 115 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 313 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 17775500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 17775500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.077437 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077437 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 56790.734824 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 56790.734824 # average ReadReq mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22127000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.tagsinuse 157.916216 # Cycle average of tags in use system.cpu.icache.tags.total_refs 3926 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 312 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 12.583333 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::.cpu.inst 157.916216 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::.cpu.inst 0.308430 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.308430 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.544922 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 8396 # Number of tag accesses system.cpu.icache.tags.data_accesses 8396 # Number of data accesses system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 22127000 # Cumulative time (in ticks) in various power states system.cpu.dtb.stage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 22127000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 22127000 # Cumulative time (in ticks) in various power states system.cpu.itb.stage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 22127000 # Cumulative time (in ticks) in various power states system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22127000 # Cumulative time (in ticks) in various power states system.cpu.dcache.demand_hits::.cpu.data 3611 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 3611 # number of demand (read+write) hits system.cpu.dcache.overall_hits::.cpu.data 3615 # number of overall hits system.cpu.dcache.overall_hits::total 3615 # number of overall hits system.cpu.dcache.demand_misses::.cpu.data 585 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 585 # number of demand (read+write) misses system.cpu.dcache.overall_misses::.cpu.data 587 # number of overall misses system.cpu.dcache.overall_misses::total 587 # number of overall misses system.cpu.dcache.demand_miss_latency::.cpu.data 32766498 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 32766498 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::.cpu.data 32766498 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 32766498 # number of overall miss cycles system.cpu.dcache.demand_accesses::.cpu.data 4196 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 4196 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::.cpu.data 4202 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 4202 # number of overall (read+write) accesses system.cpu.dcache.demand_miss_rate::.cpu.data 0.139418 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.139418 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::.cpu.data 0.139695 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.139695 # miss rate for overall accesses system.cpu.dcache.demand_avg_miss_latency::.cpu.data 56011.107692 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 56011.107692 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::.cpu.data 55820.269165 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 55820.269165 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 394 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 56.285714 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.demand_mshr_hits::.cpu.data 402 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 402 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::.cpu.data 402 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 402 # number of overall MSHR hits system.cpu.dcache.demand_mshr_misses::.cpu.data 183 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 183 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::.cpu.data 185 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 185 # number of overall MSHR misses system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 11043999 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 11043999 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 11185999 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 11185999 # number of overall MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.043613 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.043613 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.044027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.044027 # mshr miss rate for overall accesses system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 60349.721311 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 60349.721311 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 60464.859459 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 60464.859459 # average overall mshr miss latency system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.ReadReq_hits::.cpu.data 2441 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2441 # number of ReadReq hits system.cpu.dcache.ReadReq_misses::.cpu.data 183 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 183 # number of ReadReq misses system.cpu.dcache.ReadReq_miss_latency::.cpu.data 8692000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 8692000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_accesses::.cpu.data 2624 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2624 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.069741 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.069741 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 47497.267760 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 47497.267760 # average ReadReq miss latency system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 91 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 92 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 92 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 5411500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 5411500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.035061 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035061 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 58820.652174 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58820.652174 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_hits::.cpu.data 870 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits system.cpu.dcache.WriteReq_misses::.cpu.data 395 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 395 # number of WriteReq misses system.cpu.dcache.WriteReq_miss_latency::.cpu.data 24001498 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 24001498 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_accesses::.cpu.data 1265 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1265 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.312253 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.312253 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 60763.286076 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 60763.286076 # average WriteReq miss latency system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 311 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 311 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 84 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 84 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 5566499 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 5566499 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.066403 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.066403 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 66267.845238 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66267.845238 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_hits::.cpu.data 4 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 4 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_accesses::.cpu.data 6 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 6 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.333333 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.333333 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 142000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 142000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 71000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71000 # average SoftPFReq mshr miss latency system.cpu.dcache.WriteLineReq_hits::.cpu.data 300 # number of WriteLineReq hits system.cpu.dcache.WriteLineReq_hits::total 300 # number of WriteLineReq hits system.cpu.dcache.WriteLineReq_misses::.cpu.data 7 # number of WriteLineReq misses system.cpu.dcache.WriteLineReq_misses::total 7 # number of WriteLineReq misses system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 73000 # number of WriteLineReq miss cycles system.cpu.dcache.WriteLineReq_miss_latency::total 73000 # number of WriteLineReq miss cycles system.cpu.dcache.WriteLineReq_accesses::.cpu.data 307 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_accesses::total 307 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.022801 # miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_miss_rate::total 0.022801 # miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 10428.571429 # average WriteLineReq miss latency system.cpu.dcache.WriteLineReq_avg_miss_latency::total 10428.571429 # average WriteLineReq miss latency system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 7 # number of WriteLineReq MSHR misses system.cpu.dcache.WriteLineReq_mshr_misses::total 7 # number of WriteLineReq MSHR misses system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 66000 # number of WriteLineReq MSHR miss cycles system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 66000 # number of WriteLineReq MSHR miss cycles system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.022801 # mshr miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.022801 # mshr miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 9428.571429 # average WriteLineReq mshr miss latency system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 9428.571429 # average WriteLineReq mshr miss latency system.cpu.dcache.LoadLockedReq_hits::.cpu.data 13 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_misses::.cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 109000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 109000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.133333 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 54500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 54500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 1 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 50500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 50500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.066667 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.066667 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 50500 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 50500 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_hits::.cpu.data 14 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 14 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_accesses::.cpu.data 14 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 14 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22127000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.tagsinuse 108.382229 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 3828 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 186 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 20.580645 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 147000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::.cpu.data 108.382229 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::.cpu.data 0.105842 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.105842 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 186 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 136 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.181641 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 8648 # Number of tag accesses system.cpu.dcache.tags.data_accesses 8648 # Number of data accesses ---------- End Simulation Statistics ----------