---------- Begin Simulation Statistics ---------- final_tick 856867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) host_inst_rate 126513 # Simulator instruction rate (inst/s) host_mem_usage 818468 # Number of bytes of host memory used host_op_rate 154558 # Simulator op (including micro ops) rate (op/s) host_seconds 14.64 # Real time elapsed on the host host_tick_rate 58534374 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1851952 # Number of instructions simulated sim_ops 2262527 # Number of ops (including micro ops) simulated sim_seconds 0.000857 # Number of seconds simulated sim_ticks 856867000 # Number of ticks simulated system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 99.843030 # BTB Hit Percentage system.cpu.branchPred.BTBHits 205449 # Number of BTB hits system.cpu.branchPred.BTBLookups 205772 # Number of BTB lookups system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.branchPred.condIncorrect 722 # Number of conditional branches incorrect system.cpu.branchPred.condPredicted 207206 # Number of conditional branches predicted system.cpu.branchPred.indirectHits 1 # Number of indirect target hits. system.cpu.branchPred.indirectLookups 73 # Number of indirect predictor lookups. system.cpu.branchPred.indirectMisses 72 # Number of indirect misses. system.cpu.branchPred.lookups 207987 # Number of BP lookups system.cpu.branchPred.usedRAS 207 # Number of times the RAS was used to get a target. system.cpu.branchPredindirectMispredicted 33 # Number of mispredicted indirect branches. system.cpu.cc_regfile_reads 618663 # number of cc regfile reads system.cpu.cc_regfile_writes 618819 # number of cc regfile writes system.cpu.commit.amos 0 # Number of atomic instructions committed system.cpu.commit.branchMispredicts 569 # The number of times a branch was mispredicted system.cpu.commit.branches 206672 # Number of branches committed system.cpu.commit.bw_lim_events 204854 # number cycles where commit BW limit reached system.cpu.commit.commitNonSpecStalls 22 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 2528 # The number of squashed insts skipped by commit system.cpu.commit.committedInsts 1852069 # Number of instructions committed system.cpu.commit.committedOps 2262644 # Number of ops (including micro ops) committed system.cpu.commit.committed_per_cycle::samples 1689948 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.338884 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.519451 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 867221 51.32% 51.32% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 615011 36.39% 87.71% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 1124 0.07% 87.78% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 985 0.06% 87.83% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 259 0.02% 87.85% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 424 0.03% 87.87% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 48 0.00% 87.88% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 22 0.00% 87.88% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 204854 12.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 1689948 # Number of insts commited each cycle system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.function_calls 111 # Number of function calls committed. system.cpu.commit.int_insts 1441730 # Number of committed integer instructions. system.cpu.commit.loads 615315 # Number of loads committed system.cpu.commit.membars 14 # Number of memory barriers committed system.cpu.commit.op_class_0::No_OpClass 2 0.00% 0.00% # Class of committed instruction system.cpu.commit.op_class_0::IntAlu 621892 27.49% 27.49% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 3 0.00% 27.49% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 2 0.00% 27.49% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 400 0.02% 27.50% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 27.50% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 27.50% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 27.50% # Class of committed instruction system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 27.50% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 200 0.01% 27.51% # Class of committed instruction system.cpu.commit.op_class_0::FloatMisc 1 0.00% 27.51% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 27.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 11 0.00% 27.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 27.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdAlu 8 0.00% 27.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdCmp 8 0.00% 27.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdCvt 0 0.00% 27.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdMisc 9 0.00% 27.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdMult 0 0.00% 27.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 27.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdShift 0 0.00% 27.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 27.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdDiv 0 0.00% 27.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 27.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAdd 409400 18.09% 45.61% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 45.61% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 45.61% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 45.61% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 204700 9.05% 54.65% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 54.65% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 54.65% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.65% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.65% # Class of committed instruction system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 54.65% # Class of committed instruction system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 54.65% # Class of committed instruction system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 54.65% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 54.65% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 54.65% # Class of committed instruction system.cpu.commit.op_class_0::SimdAes 0 0.00% 54.65% # Class of committed instruction system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 54.65% # Class of committed instruction system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 54.65% # Class of committed instruction system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 54.65% # Class of committed instruction system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 54.65% # Class of committed instruction system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 54.65% # Class of committed instruction system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 54.65% # Class of committed instruction system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 54.65% # Class of committed instruction system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 54.65% # Class of committed instruction system.cpu.commit.op_class_0::MemRead 615315 27.19% 81.85% # Class of committed instruction system.cpu.commit.op_class_0::MemWrite 410693 18.15% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 2262644 # Class of committed instruction system.cpu.commit.refs 1026008 # Number of memory references committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.vec_insts 1638883 # Number of committed Vector instructions. system.cpu.committedInsts 1851952 # Number of Instructions Simulated system.cpu.committedOps 2262527 # Number of Ops (including micro ops) Simulated system.cpu.cpi 0.925367 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.925367 # CPI: Total CPI of All Threads system.cpu.decode.BlockedCycles 38361 # Number of cycles decode is blocked system.cpu.decode.BranchMispred 158 # Number of times decode detected a branch misprediction system.cpu.decode.BranchResolved 205468 # Number of times decode resolved a branch system.cpu.decode.DecodedInsts 2267445 # Number of instructions handled by decode system.cpu.decode.IdleCycles 622807 # Number of cycles decode is idle system.cpu.decode.RunCycles 1025603 # Number of cycles decode is running system.cpu.decode.SquashCycles 579 # Number of cycles decode is squashing system.cpu.decode.SquashedInsts 1565 # Number of squashed instructions handled by decode system.cpu.decode.UnblockCycles 3287 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.fetch.Branches 207987 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 619691 # Number of cache lines fetched system.cpu.fetch.Cycles 1061446 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 362 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 1858905 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 1464 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.121365 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 628459 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 205657 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 1.084710 # Number of inst fetches per cycle system.cpu.fetch.rateDist::samples 1690637 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.342969 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 1.222046 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 658165 38.93% 38.93% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 208216 12.32% 51.25% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 410511 24.28% 75.53% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 413745 24.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 1690637 # Number of instructions fetched each cycle (Total) system.cpu.idleCycles 23098 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.branchMispredicts 589 # Number of branch mispredicts detected at execute system.cpu.iew.exec_branches 206897 # Number of branches executed system.cpu.iew.exec_nop 136 # number of nop insts executed system.cpu.iew.exec_rate 1.321218 # Inst execution rate system.cpu.iew.exec_refs 1026455 # number of memory reference insts executed system.cpu.iew.exec_stores 410811 # Number of stores executed system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 110 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 616044 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 410963 # Number of dispatched store instructions system.cpu.iew.iewDispatchedInsts 2265624 # Number of instructions dispatched to IQ system.cpu.iew.iewExecLoadInsts 615644 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 706 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecutedInsts 2264217 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 93 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 579 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 92 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread0.forwLoads 12 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.memOrderViolation 3 # Number of memory ordering violations system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.squashedLoads 729 # Number of loads squashed system.cpu.iew.lsq.thread0.squashedStores 270 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 3 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 485 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 104 # Number of branches that were predicted taken incorrectly system.cpu.iew.wb_consumers 2258648 # num instructions consuming a value system.cpu.iew.wb_count 2263970 # cumulative count of insts written-back system.cpu.iew.wb_fanout 0.726701 # average fanout of values written-back system.cpu.iew.wb_producers 1641362 # num instructions producing a value system.cpu.iew.wb_rate 1.321074 # insts written-back per cycle system.cpu.iew.wb_sent 2264038 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 1651304 # number of integer regfile reads system.cpu.int_regfile_writes 417292 # number of integer regfile writes system.cpu.ipc 1.080652 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.080652 # IPC: Total IPC of All Threads system.cpu.iq.FU_type_0::No_OpClass 2 0.00% 0.00% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 623335 27.52% 27.52% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 3 0.00% 27.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 2 0.00% 27.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 400 0.02% 27.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 27.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 27.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 27.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 27.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 200 0.01% 27.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatMisc 1 0.00% 27.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 27.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 11 0.00% 27.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 27.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 8 0.00% 27.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 8 0.00% 27.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 27.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 9 0.00% 27.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 27.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 27.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 27.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 27.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 27.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 27.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 409400 18.08% 45.63% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.63% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 45.63% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 45.63% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 204700 9.04% 54.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 54.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 54.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 54.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 54.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 54.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdAes 0 0.00% 54.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 54.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 54.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 54.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 54.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 54.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 54.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 54.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 54.66% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 615984 27.20% 81.86% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 410860 18.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 2264923 # Type of FU issued system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fu_busy_cnt 411395 # FU busy when requested system.cpu.iq.fu_busy_rate 0.181638 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 444 0.11% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMisc 0 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 2 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 2 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::SimdDiv 0 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.11% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 388 0.09% 0.20% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.20% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.20% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.20% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.20% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.20% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.20% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.20% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.20% # attempts to use FU when none available system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 0.20% # attempts to use FU when none available system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 0.20% # attempts to use FU when none available system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 0.20% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 0.20% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 0.20% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAes 0 0.00% 0.20% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAesMix 0 0.00% 0.20% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 0.20% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 0.20% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 0.20% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 0.20% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 0.20% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 0.20% # attempts to use FU when none available system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 0.20% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 204705 49.76% 49.96% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 205854 50.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 627035 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 2943588 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 625087 # Number of integer instruction queue wakeup accesses system.cpu.iq.int_inst_queue_writes 629134 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 2265458 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 2264923 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqSquashedInstsExamined 2960 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 79 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 2043 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.issued_per_cycle::samples 1690637 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.339686 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 0.720766 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 247384 14.63% 14.63% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 623722 36.89% 51.53% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 817410 48.35% 99.87% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 2103 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 18 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 1690637 # Number of insts issued each cycle system.cpu.iq.rate 1.321630 # Inst issue rate system.cpu.iq.vec_alu_accesses 2049281 # Number of vector alu accesses system.cpu.iq.vec_inst_queue_reads 3688369 # Number of vector instruction queue reads system.cpu.iq.vec_inst_queue_wakeup_accesses 1638883 # Number of vector instruction queue wakeup accesses system.cpu.iq.vec_inst_queue_writes 1639317 # Number of vector instruction queue writes system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.hits 0 # DTB hits system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.misses 0 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 616044 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 410963 # Number of stores inserted to the mem dependence unit. system.cpu.misc_regfile_reads 11998375 # number of misc regfile reads system.cpu.misc_regfile_writes 614757 # number of misc regfile writes system.cpu.numCycles 1713735 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.BlockCycles 30084 # Number of cycles rename is blocking system.cpu.rename.CommittedMaps 2878532 # Number of HB maps that are committed system.cpu.rename.IdleCycles 625451 # Number of cycles rename is idle system.cpu.rename.LQFullEvents 889 # Number of times rename has blocked due to LQ full system.cpu.rename.ROBFullEvents 3183 # Number of times rename has blocked due to ROB full system.cpu.rename.RenameLookups 7805864 # Number of register rename lookups that rename has made system.cpu.rename.RenamedInsts 2266354 # Number of instructions processed by rename system.cpu.rename.RenamedOperands 2882571 # Number of destination operands rename has renamed system.cpu.rename.RunCycles 1025874 # Number of cycles rename is running system.cpu.rename.SQFullEvents 1558 # Number of times rename has blocked due to SQ full system.cpu.rename.SquashCycles 579 # Number of cycles rename is squashing system.cpu.rename.SquashedInsts 463 # Number of squashed instructions processed by rename system.cpu.rename.UnblockCycles 6719 # Number of cycles rename is unblocking system.cpu.rename.UndoneMaps 4039 # Number of HB maps that are undone due to squashing system.cpu.rename.int_rename_lookups 1653204 # Number of integer rename lookups system.cpu.rename.serializeStallCycles 1930 # count of cycles rename stalled for serializing inst system.cpu.rename.serializingInsts 59 # count of serializing insts renamed system.cpu.rename.skidInsts 7115 # count of insts added to the skid buffer system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed system.cpu.rename.vec_rename_lookups 1639528 # Number of vector rename lookups system.cpu.rob.rob_reads 3750175 # The number of ROB reads system.cpu.rob.rob_writes 4531034 # The number of ROB writes system.cpu.timesIdled 270 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.vec_regfile_reads 1639101 # number of vector regfile reads system.cpu.vec_regfile_writes 1229340 # number of vector regfile writes system.cpu.workload.numSyscalls 7 # Number of system calls system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_single_requests 47 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.tot_requests 1069 # Total number of requests made to the snoop filter. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.pwrStateResidencyTicks::UNDEFINED 856867000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 932 # Transaction distribution system.membus.trans_dist::WritebackDirty 2 # Transaction distribution system.membus.trans_dist::WritebackClean 43 # Transaction distribution system.membus.trans_dist::ReadExReq 84 # Transaction distribution system.membus.trans_dist::ReadExResp 84 # Transaction distribution system.membus.trans_dist::ReadCleanReq 330 # Transaction distribution system.membus.trans_dist::ReadSharedReq 603 # Transaction distribution system.membus.trans_dist::InvalidateReq 7 # Transaction distribution system.membus.pkt_count_system.cpu.icache.mem_side::system.mem_ctrls.port 702 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.dcache.mem_side::system.mem_ctrls.port 1383 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 2085 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.icache.mem_side::system.mem_ctrls.port 23808 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.dcache.mem_side::system.mem_ctrls.port 44096 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 67904 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 1024 # Request fanout histogram system.membus.snoop_fanout::mean 0.001953 # Request fanout histogram system.membus.snoop_fanout::stdev 0.044173 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 1022 99.80% 99.80% # Request fanout histogram system.membus.snoop_fanout::1 2 0.20% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 1024 # Request fanout histogram system.membus.reqLayer0.occupancy 1399000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) system.membus.respLayer1.occupancy 1750000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 3622250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.4 # Layer utilization (%) system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.cpu_voltage_domain.voltage 1 # Voltage in Volts system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 856867000 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::.cpu.inst 21056 # Number of bytes read from this memory system.mem_ctrls.bytes_read::.cpu.data 43968 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 65024 # Number of bytes read from this memory system.mem_ctrls.bytes_inst_read::.cpu.inst 21056 # Number of instructions bytes read from this memory system.mem_ctrls.bytes_inst_read::total 21056 # Number of instructions bytes read from this memory system.mem_ctrls.bytes_written::.writebacks 128 # Number of bytes written to this memory system.mem_ctrls.bytes_written::total 128 # Number of bytes written to this memory system.mem_ctrls.num_reads::.cpu.inst 329 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::.cpu.data 687 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::total 1016 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::.writebacks 2 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 2 # Number of write requests responded to by this memory system.mem_ctrls.bw_read::.cpu.inst 24573242 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::.cpu.data 51312514 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::total 75885756 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_inst_read::.cpu.inst 24573242 # Instruction read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_inst_read::total 24573242 # Instruction read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_write::.writebacks 149381 # Write bandwidth from this memory (bytes/s) system.mem_ctrls.bw_write::total 149381 # Write bandwidth from this memory (bytes/s) system.mem_ctrls.bw_total::.writebacks 149381 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::.cpu.inst 24573242 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::.cpu.data 51312514 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::total 76035137 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.avgPriority_.writebacks::samples 45.00 # Average QoS priority value for accepted requests system.mem_ctrls.avgPriority_.cpu.inst::samples 328.00 # Average QoS priority value for accepted requests system.mem_ctrls.avgPriority_.cpu.data::samples 687.00 # Average QoS priority value for accepted requests system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) system.mem_ctrls.priorityMaxLatency 0.001702218500 # per QoS priority maximum request to response latency (s) system.mem_ctrls.numReadWriteTurnArounds 1 # Number of turnarounds from READ to WRITE system.mem_ctrls.numWriteReadTurnArounds 1 # Number of turnarounds from WRITE to READ system.mem_ctrls.numStayReadState 2261 # Number of times bus staying in READ state system.mem_ctrls.numStayWriteState 15 # Number of times bus staying in WRITE state system.mem_ctrls.readReqs 1017 # Number of read requests accepted system.mem_ctrls.writeReqs 45 # Number of write requests accepted system.mem_ctrls.readBursts 1017 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 45 # Number of DRAM write bursts, including those merged in the write queue system.mem_ctrls.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 182 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 132 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 42 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 6 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 29 # Per bank write bursts system.mem_ctrls.perBankRdBursts::7 39 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 53 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 24 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 39 # Per bank write bursts system.mem_ctrls.perBankRdBursts::11 85 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 72 # Per bank write bursts system.mem_ctrls.perBankRdBursts::13 52 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 128 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 131 # Per bank write bursts system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 2 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 8 # Per bank write bursts system.mem_ctrls.perBankWrBursts::11 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::13 3 # Per bank write bursts system.mem_ctrls.perBankWrBursts::14 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.avgRdQLen 1.03 # Average read queue length when enqueuing system.mem_ctrls.avgWrQLen 18.70 # Average write queue length when enqueuing system.mem_ctrls.totQLat 8270000 # Total ticks spent queuing system.mem_ctrls.totBusLat 5075000 # Total ticks spent in databus transfers system.mem_ctrls.totMemAccLat 27301250 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrls.avgQLat 8147.78 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst system.mem_ctrls.avgMemAccLat 26897.78 # Average memory access latency per DRAM burst system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry system.mem_ctrls.readRowHits 857 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 11 # Number of row buffer hits during writes system.mem_ctrls.readRowHitRate 84.43 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 24.44 # Row buffer hit rate for writes system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::6 1017 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 45 # Write request sizes (log2) system.mem_ctrls.rdQLenPdf::0 590 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 351 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 52 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 16 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 6 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::17 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::18 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::19 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::20 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::21 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::22 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::23 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::24 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::25 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::26 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::27 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::28 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::29 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::30 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::31 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::32 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrls.bytesPerActivate::samples 161 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::mean 409.043478 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::gmean 246.147657 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::stdev 379.855899 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::0-127 42 26.09% 26.09% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::128-255 34 21.12% 47.20% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::256-383 26 16.15% 63.35% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::384-511 8 4.97% 68.32% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::512-639 6 3.73% 72.05% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::640-767 2 1.24% 73.29% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::768-895 4 2.48% 75.78% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::896-1023 2 1.24% 77.02% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::1024-1151 37 22.98% 100.00% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::total 161 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::mean 989 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::gmean 989.000000 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::stdev nan # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::960-991 1 100.00% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 1 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 1 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads system.mem_ctrls.bytesReadDRAM 64960 # Total number of bytes read from DRAM system.mem_ctrls.bytesReadWrQ 128 # Total number of bytes read from write queue system.mem_ctrls.bytesWritten 1024 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 65088 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 2880 # Total written bytes from the system interface side system.mem_ctrls.avgRdBW 75.81 # Average DRAM read bandwidth in MiByte/s system.mem_ctrls.avgWrBW 1.20 # Average achieved write bandwidth in MiByte/s system.mem_ctrls.avgRdBWSys 75.96 # Average system read bandwidth in MiByte/s system.mem_ctrls.avgWrBWSys 3.36 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrls.busUtil 0.60 # Data bus utilization in percentage system.mem_ctrls.busUtilRead 0.59 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.mem_ctrls.totGap 856858500 # Total gap between requests system.mem_ctrls.avgGap 806834.75 # Average gap between requests system.mem_ctrls.masterReadBytes::.cpu.inst 20992 # Per-master bytes read from memory system.mem_ctrls.masterReadBytes::.cpu.data 43968 # Per-master bytes read from memory system.mem_ctrls.masterWriteBytes::.writebacks 1024 # Per-master bytes write to memory system.mem_ctrls.masterReadRate::.cpu.inst 24498551.117034498602 # Per-master bytes read from memory rate (Bytes/sec) system.mem_ctrls.masterReadRate::.cpu.data 51312514.077447257936 # Per-master bytes read from memory rate (Bytes/sec) system.mem_ctrls.masterWriteRate::.writebacks 1195051.274001682876 # Per-master bytes write to memory rate (Bytes/sec) system.mem_ctrls.masterReadAccesses::.cpu.inst 330 # Per-master read serviced memory accesses system.mem_ctrls.masterReadAccesses::.cpu.data 687 # Per-master read serviced memory accesses system.mem_ctrls.masterWriteAccesses::.writebacks 45 # Per-master write serviced memory accesses system.mem_ctrls.masterReadTotalLat::.cpu.inst 9127000 # Per-master read total memory access latency system.mem_ctrls.masterReadTotalLat::.cpu.data 18174250 # Per-master read total memory access latency system.mem_ctrls.masterWriteTotalLat::.writebacks 10118502500 # Per-master write total memory access latency system.mem_ctrls.masterReadAvgLat::.cpu.inst 27657.58 # Per-master read average memory access latency system.mem_ctrls.masterReadAvgLat::.cpu.data 26454.51 # Per-master read average memory access latency system.mem_ctrls.masterWriteAvgLat::.writebacks 224855611.11 # Per-master write average memory access latency system.mem_ctrls.pageHitRate 81.89 # Row buffer hit rate, read and write combined system.mem_ctrls.rank1.actEnergy 799680 # Energy for activate commands per rank (pJ) system.mem_ctrls.rank1.preEnergy 421245 # Energy for precharge commands per rank (pJ) system.mem_ctrls.rank1.readEnergy 4162620 # Energy for read commands per rank (pJ) system.mem_ctrls.rank1.writeEnergy 83520 # Energy for write commands per rank (pJ) system.mem_ctrls.rank1.refreshEnergy 67610400.000000 # Energy for refresh commands per rank (pJ) system.mem_ctrls.rank1.actBackEnergy 30740100 # Energy for active background per rank (pJ) system.mem_ctrls.rank1.preBackEnergy 303150720 # Energy for precharge background per rank (pJ) system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.mem_ctrls.rank1.totalEnergy 406968285 # Total energy per rank (pJ) system.mem_ctrls.rank1.averagePower 474.949187 # Core power per rank (mW) system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank system.mem_ctrls.rank1.memoryStateTime::IDLE 787748000 # Time in different power states system.mem_ctrls.rank1.memoryStateTime::REF 28600000 # Time in different power states system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls.rank1.memoryStateTime::ACT 40519000 # Time in different power states system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrls.rank0.actEnergy 364140 # Energy for activate commands per rank (pJ) system.mem_ctrls.rank0.preEnergy 189750 # Energy for precharge commands per rank (pJ) system.mem_ctrls.rank0.readEnergy 3077340 # Energy for read commands per rank (pJ) system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrls.rank0.refreshEnergy 67610400.000000 # Energy for refresh commands per rank (pJ) system.mem_ctrls.rank0.actBackEnergy 32370870 # Energy for active background per rank (pJ) system.mem_ctrls.rank0.preBackEnergy 301777440 # Energy for precharge background per rank (pJ) system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.mem_ctrls.rank0.totalEnergy 405389940 # Total energy per rank (pJ) system.mem_ctrls.rank0.averagePower 473.107192 # Core power per rank (mW) system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank system.mem_ctrls.rank0.memoryStateTime::IDLE 784157500 # Time in different power states system.mem_ctrls.rank0.memoryStateTime::REF 28600000 # Time in different power states system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls.rank0.memoryStateTime::ACT 44109500 # Time in different power states system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.pwrStateResidencyTicks::ON 856867000 # Cumulative time (in ticks) in various power states system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 856867000 # Cumulative time (in ticks) in various power states system.cpu.icache.demand_hits::.cpu.inst 619252 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 619252 # number of demand (read+write) hits system.cpu.icache.overall_hits::.cpu.inst 619252 # number of overall hits system.cpu.icache.overall_hits::total 619252 # number of overall hits system.cpu.icache.demand_misses::.cpu.inst 439 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 439 # number of demand (read+write) misses system.cpu.icache.overall_misses::.cpu.inst 439 # number of overall misses system.cpu.icache.overall_misses::total 439 # number of overall misses system.cpu.icache.demand_miss_latency::.cpu.inst 24027000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 24027000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::.cpu.inst 24027000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 24027000 # number of overall miss cycles system.cpu.icache.demand_accesses::.cpu.inst 619691 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 619691 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::.cpu.inst 619691 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 619691 # number of overall (read+write) accesses system.cpu.icache.demand_miss_rate::.cpu.inst 0.000708 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000708 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::.cpu.inst 0.000708 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000708 # miss rate for overall accesses system.cpu.icache.demand_avg_miss_latency::.cpu.inst 54731.207289 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 54731.207289 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::.cpu.inst 54731.207289 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 54731.207289 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::.writebacks 43 # number of writebacks system.cpu.icache.writebacks::total 43 # number of writebacks system.cpu.icache.demand_mshr_hits::.cpu.inst 109 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 109 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::.cpu.inst 109 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 109 # number of overall MSHR hits system.cpu.icache.demand_mshr_misses::.cpu.inst 330 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 330 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::.cpu.inst 330 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 330 # number of overall MSHR misses system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 19515500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 19515500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 19515500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 19515500 # number of overall MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.000533 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000533 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.000533 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000533 # mshr miss rate for overall accesses system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 59137.878788 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 59137.878788 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 59137.878788 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 59137.878788 # average overall mshr miss latency system.cpu.icache.replacements 43 # number of replacements system.cpu.icache.ReadReq_hits::.cpu.inst 619252 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 619252 # number of ReadReq hits system.cpu.icache.ReadReq_misses::.cpu.inst 439 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 439 # number of ReadReq misses system.cpu.icache.ReadReq_miss_latency::.cpu.inst 24027000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 24027000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_accesses::.cpu.inst 619691 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 619691 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.000708 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000708 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 54731.207289 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 54731.207289 # average ReadReq miss latency system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 109 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 109 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 330 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 330 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 19515500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 19515500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.000533 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000533 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 59137.878788 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59137.878788 # average ReadReq mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 856867000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.tagsinuse 242.614246 # Cycle average of tags in use system.cpu.icache.tags.total_refs 619581 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 329 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1883.224924 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::.cpu.inst 242.614246 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::.cpu.inst 0.473856 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.473856 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 286 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 220 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.558594 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1239711 # Number of tag accesses system.cpu.icache.tags.data_accesses 1239711 # Number of data accesses system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 856867000 # Cumulative time (in ticks) in various power states system.cpu.dtb.stage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 856867000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 856867000 # Cumulative time (in ticks) in various power states system.cpu.itb.stage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 856867000 # Cumulative time (in ticks) in various power states system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 856867000 # Cumulative time (in ticks) in various power states system.cpu.dcache.demand_hits::.cpu.data 1122948 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 1122948 # number of demand (read+write) hits system.cpu.dcache.overall_hits::.cpu.data 1122952 # number of overall hits system.cpu.dcache.overall_hits::total 1122952 # number of overall hits system.cpu.dcache.demand_misses::.cpu.data 5700 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 5700 # number of demand (read+write) misses system.cpu.dcache.overall_misses::.cpu.data 5702 # number of overall misses system.cpu.dcache.overall_misses::total 5702 # number of overall misses system.cpu.dcache.demand_miss_latency::.cpu.data 284501498 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 284501498 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::.cpu.data 284501498 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 284501498 # number of overall miss cycles system.cpu.dcache.demand_accesses::.cpu.data 1128648 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 1128648 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::.cpu.data 1128654 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 1128654 # number of overall (read+write) accesses system.cpu.dcache.demand_miss_rate::.cpu.data 0.005050 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.005050 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::.cpu.data 0.005052 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.005052 # miss rate for overall accesses system.cpu.dcache.demand_avg_miss_latency::.cpu.data 49912.543509 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 49912.543509 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::.cpu.data 49895.036478 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 49895.036478 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 505 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 42.083333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::.writebacks 2 # number of writebacks system.cpu.dcache.writebacks::total 2 # number of writebacks system.cpu.dcache.demand_mshr_hits::.cpu.data 5009 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 5009 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::.cpu.data 5009 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 5009 # number of overall MSHR hits system.cpu.dcache.demand_mshr_misses::.cpu.data 691 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 691 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::.cpu.data 693 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 693 # number of overall MSHR misses system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 39608500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 39608500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 39750500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 39750500 # number of overall MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.000612 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000612 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.000614 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000614 # mshr miss rate for overall accesses system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 57320.549928 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 57320.549928 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 57360.028860 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 57360.028860 # average overall mshr miss latency system.cpu.dcache.replacements 2 # number of replacements system.cpu.dcache.ReadReq_hits::.cpu.data 712679 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 712679 # number of ReadReq hits system.cpu.dcache.ReadReq_misses::.cpu.data 5290 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 5290 # number of ReadReq misses system.cpu.dcache.ReadReq_miss_latency::.cpu.data 259553000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 259553000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_accesses::.cpu.data 717969 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 717969 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.007368 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.007368 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 49064.839319 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 49064.839319 # average ReadReq miss latency system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 4690 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 4690 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 600 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 600 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 33567000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 33567000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.000836 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000836 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 55945 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55945 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_hits::.cpu.data 410269 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 410269 # number of WriteReq hits system.cpu.dcache.WriteReq_misses::.cpu.data 403 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 403 # number of WriteReq misses system.cpu.dcache.WriteReq_miss_latency::.cpu.data 24875498 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 24875498 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_accesses::.cpu.data 410672 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 410672 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.000981 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000981 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 61725.801489 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 61725.801489 # average WriteReq miss latency system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 319 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 319 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 84 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 84 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 5975500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 5975500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.000205 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000205 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 71136.904762 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71136.904762 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_hits::.cpu.data 4 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 4 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_accesses::.cpu.data 6 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 6 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.333333 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.333333 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 142000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 142000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 71000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71000 # average SoftPFReq mshr miss latency system.cpu.dcache.WriteLineReq_misses::.cpu.data 7 # number of WriteLineReq misses system.cpu.dcache.WriteLineReq_misses::total 7 # number of WriteLineReq misses system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 73000 # number of WriteLineReq miss cycles system.cpu.dcache.WriteLineReq_miss_latency::total 73000 # number of WriteLineReq miss cycles system.cpu.dcache.WriteLineReq_accesses::.cpu.data 7 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_accesses::total 7 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 10428.571429 # average WriteLineReq miss latency system.cpu.dcache.WriteLineReq_avg_miss_latency::total 10428.571429 # average WriteLineReq miss latency system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 7 # number of WriteLineReq MSHR misses system.cpu.dcache.WriteLineReq_mshr_misses::total 7 # number of WriteLineReq MSHR misses system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 66000 # number of WriteLineReq MSHR miss cycles system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 66000 # number of WriteLineReq MSHR miss cycles system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 9428.571429 # average WriteLineReq mshr miss latency system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 9428.571429 # average WriteLineReq mshr miss latency system.cpu.dcache.LoadLockedReq_hits::.cpu.data 16 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 16 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_misses::.cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 138500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 138500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 18 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 18 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.111111 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111111 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 69250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 1 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 78000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 78000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.055556 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.055556 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 78000 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 78000 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_hits::.cpu.data 14 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 14 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_accesses::.cpu.data 14 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 14 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 856867000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.tagsinuse 653.667461 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1123676 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 694 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 1619.129683 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 147000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::.cpu.data 653.667461 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::.cpu.data 0.638347 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.638347 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 692 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 671 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.675781 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 2258066 # Number of tag accesses system.cpu.dcache.tags.data_accesses 2258066 # Number of data accesses ---------- End Simulation Statistics ----------